MXXXXXXX ND NG NS NB MNAME <L=VAL> <W=VAL> <AD=VAL> <AS=VAL>
+ <PD=VAL> <PS=VAL> <NRD=VAL> <NRS=VAL> <OFF>
+ <IC=VDS, VGS, VBS> <TEMP=T>
Additional Information
More details can be found in the HyperSpice chapter in Extended Definitions for Advanced Users.M1 24 2 0 20 TYPE1
M31 2 17 6 10 MODM L=5U W=2U
M1 2 9 3 0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U
The MOSFET transistor also called MOS is a Metal Oxide Semiconductor Field Effect Transistor. It is the most used inside the microelectronic field and is the based component for logic gates definitions.
ND, NG, NS, and NB are the drain, gate, source, and bulk (substrate) nodes, respectively.
MNAME is the model name.
L and W are the channel length and width, in meters.
AD and AS are the areas of the drain and source diffusions, in . Note that the suffix U specifies microns (1e-6 m) and P square-microns (1e-12 ).
If any of L, W, AD, or AS are not specified, default values are used. The use of defaults simplifies input file preparation, as well as the editing required if device geometries are to be changed.
PD and PS are the perimeters of the drain and source junctions, in meters.
RD and NRS designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance RSH specified on the .MODEL control line for an accurate representation of the parasitic series drain and source resistance of each transistor.
PD and PS default to 0.0 while NRD and NRS to 1.0.
OFF indicates an (optional) initial condition on the device for dc analysis. The (optional) initial condition specification using IC=VDS, VGS, VBS is intended for use with the UIC option on the .TRAN control line, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC control line for a better and more convenient way to specify transient initial conditions. The (optional) TEMP value is the temperature at which this device is to operate, and overrides the temperature specification on the .OPTION control line. The temperature specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for level 4 or 5 (BSIM) devices.
.MODEL MOSMNAME <PMOS|NMOS> LEVEL=<level number> <PARAMETER=<VALUE>>
| Level number | Mos type |
|---|---|
| 0, 1 | Mos Level 1 |
| 2 | Mos Level 2 |
| 3 | Mos Level 3 |
| 13 | Bsim1 |
| 39 | Bsim2 |
| 49, 53 | Bsim3 v3.3(.2) |
These parameters are computed by SPICE if process parameters (NSUB, TOX, ...) are given, but user-specified values always override.
VTO is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices. Charge storage is modeled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap capacitances, by the nonlinear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction voltage respectively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB.
Charge storage effects are modeled by the piecewise linear voltages-dependent capacitance model proposed by Meyer. The thin-oxide charge-storage effects are treated slightly different for the LEVEL=1 model. These voltage-dependent capacitances are included only if TOX is specified in the input description and they are represented using Meyer's formulation. There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as IS (in A) or as JS (in A/). Whereas the first is an absolute value the second is multiplied by AD and AS to give the reverse current of the drain and source junctions respectively. This methodology has been chosen since there is no sense in relating always junction characteristics with AD and AS entered on the device line; the areas can be defaulted. The same idea applies also to the zero-bias junction capacitances CBD and CBS (in F) on one hand, and CJ (in F/) on the other.
The parasitic drain and source series resistance can be expressed as either RD and RS (in ohms) or RSH (in Ω/sq.), the latter being multiplied by the number of squares NRD and NRS input on the device line.
SPICE level 1, 2, 3 parameters:
| name | parameter | units | default | example | |
|---|---|---|---|---|---|
| 1 | LEVEL | model | index | - | 1 |
| 2 | VTO | zero-bias threshold voltage (VT0) | V | 0.0 | 1.0 |
| 3 | KP | transconductance parameter | A/ | 2.0e-5 | 3.1e-5 |
| 4 | GAMMA | bulk threshold parameter () | 0.0 | 0.37 | |
| 5 | PHI | surface potential () | V | 0.6 | 0.65 |
| 6 | LAMBDA | channel-length modulation | 1/V | 0.0 | 0.02 |
| MOS1 and MOS2 only | |||||
| 7 | RD | drain ohmic resistance | Ω | 0.0 | 1.0 |
| 8 | RS | source ohmic resistance | Ω | 0.0 | 1.0 |
| 9 | CBD | zero-bias B-D junction capacitance | F | 0.0 | 20fF |
| 10 | CBS | zero-bias B-S junction capacitance | F | 0.0 | 20fF |
| 11 | IS | bulk junction saturation current (IS) | A | 1.0e-14 | 1.0e-15 |
| 12 | PB | bulk junction potential | V | 0.8 | 0.87 |
| 13 | CGSO | gate-source overlap capacitance | F/m | 0.0 | 4.0e-11 |
| per meter channel width | |||||
| 14 | CGDO | gate-drain overlap capacitance | F/m | 0.0 | 4.0e-11 |
| per meter channel width | |||||
| 15 | CGBO | gate-bulk overlap capacitance | F/m | 0.0 | 2.0e-10 |
| per meter channel length | |||||
| 16 | RSH | drain and source diffusion | Ω/q | 0.0 | 10.0 |
| sheet resistance | |||||
| 17 | CJ | zero-bias bulk junction bottom cap. | F/ | 0.0 | 2.0e-4 |
| per sq-meter of junction area | |||||
| 18 | MJ | bulk junction bottom grading coeff. | - | 0.5 | 0.5 |
| 19 | CJSW | zero-bias bulk junction sidewall cap. | F/m | 0.0 | 1.0e-9 |
| per meter of junction perimeter | |||||
| 20 | MJSW | bulk junction sidewall grading coeff. | - | 0.50(level1) | |
| 0.33(level2,3) | |||||
| 21 | JS | bulk junction saturation current | A/ | 1.0e-8 | |
| per sq-meter of junction area | |||||
| 22 | TOX | oxide thickness | meter | 1.0e-7 | 1.0e-7 |
| 23 | NSUB | substrate doping | 1/cm3 | 0.0 | 4.0e15 |
| 24 | NSS | surface state density | 1/c | 0.0 | 1.0e10 |
| 25 | NFS | fast surface state density | 1/c | 0.0 | 1.0e10 |
| 26 | TPG | type of gate material: | - | 1.0 | |
| +1 opp. to substrate | |||||
| -1 same as substrate | |||||
| 0 Al gate | |||||
| 27 | XJ | metallurgical junction depth | meter | 0.0 | 1 |
| 28 | LD | lateral diffusion | meter | 0.0 | 0.8 |
| 29 | UO | surface mobility | c/Vs | 600 | 700 |
| 30 | UCRIT | critical field for mobility | V/cm | 1.0e4 | 1.0e4 |
| degradation (MOS2 only) | |||||
| 31 | UEXP | critical field exponent in | - | 0.0 | 0.1 |
| mobility degradation (MOS2 only) | |||||
| 32 | UTRA | transverse field coeff. (mobility) | - | 0.0 | 0.3 |
| (deleted for MOS2) | |||||
| 33 | VMAX | maximum drift velocity of carriers | m/s | 0.0 | 5.0e4 |
| 34 | NEFF | total channel-charge (fixed and | - | 1.0 | 5.0 |
| mobile) coefficient (MOS2 only) | |||||
| 35 | KF | flicker noise coefficient | - | 0.0 | 1.0e-26 |
| 36 | AF | flicker noise exponent | - | 1.0 | 1.2 |
| 37 | FC | coefficient for forward-bias | - | 0.5 | |
| depletion capacitance formula | |||||
| 38 | DELTA | width effect on threshold voltage | - | 0.0 | 1.0 |
| (MOS2 and MOS3) | |||||
| 39 | THETA | mobility modulation (MOS3 only) | 1/V | 0.0 | 0.1 |
| 40 | ETA | static feedback (MOS3 only) | - | 0.0 | 1.0 |
| 41 | KAPPA | saturation field factor (MOS3 only) | - | 0.2 | 0.5 |
| 42 | TNOM | parameter measurement temperature | C | 27 | 50 |