Altair PollEx 2022.3 Release Notes


  • Added a Technical Cleanliness menu to inspect and analyze contamination and ensure cleanliness from particles on a PCB board.

  • Beta release of Siemens Xpedition importer directly from its binary data by using the API.

  • Added to support the IBIS-AMI model for SerDes analysis in SI.

  • Modified the Radiated Emission analysis of the SI to process automatically using the Feko Lua script. The process of performing radiated emission analysis in PollEx and using the result to perform Near Field Radiation analysis in Feko is automatically performed.

New Features

PollEx Modeler
  • Added a function to import and export Power Information (such as voltage, current, and target impedance) in Excel format in the Electrical & Thermal Properties dialog of Parts. This feature enables users to set manually power information without an IBIS model.
PollEx Verification
Logic DFE
  • Added a function to set Net Group using Net Property information.
PollEx Analysis
  • Added a function in the Net Topology to calculate and display capacitance for each segment of the net. This function can be used as intermediate data when calculating the total capacitance of the net or implementing the radiated emission function.
  • Added a button for Update Part Information in the Part dialog of PollEx PCB that allows PCB part modification to be reflected in the PI Analyzer to run the what-if simulation.
  • Added a menu to report all setting parameters in the PI Analyzer (PIA) to Excel, such as Parts, PCB stack-up, Simulation model, port information, and voltage/current information.
  • Added a function to change "port grouping" after executing port grouping in PI PDN Analysis. This function allows changing the port group on the PIA after the ports are grouped by selecting the "Port Grouping" option in Constraints.


PollEx Modeler
  • Modified the Board Information to display the correct PDBB saved version.
  • Enhanced to display only differences on the comparison of the Link and Search.
PollEx Verification
  • Enhanced the local web help to open the DFM, DFA, DFE, DFE+, and Logic DFE items you are viewing when pressing the F1 key.
  • Modified the Component Classification Setting in DFM and DFA to display used checking item names when deleting groups.
  • Added an option to retain user-defined comments in a particular column for the User Defined Excel Format export.
  • Added an option in the Drill Scan item to check the smallest and largest drill size.
  • Added a tolerance option in the Via Location Setting section of the BGA item.
  • Added an option in the Copper Connected Pad item to check the number of tie legs connected to the component pad.
  • Added an option in the Guide Hole item to allow random location if the guide hole is matched with the PCB datum (0,0).
  • Modified the via violation result of Via Spacing 2 and Via Annular Ring items to display the start and end layers of the violated via.
  • Modified the U Name Overlap item to detect a violation for the opposite placed reference name from the component.
  • Modified violation display for the pads connected with copper polygons in the Connected Pad item.
  • Added an option in the Differential Pair Net item to check whether the PAD fill-cut of the passive component connected to the High-speed Differential Pair net.
  • Modified the nut shape check option in the Differential Pair Net item to check not only the nut shape but also the distance between the PAD and shield.
PollEx Analysis
  • Modified the Parts dialog in the PI Analyzer (PIA) to display component simulation model information such as Model Type, Model File, and Model Name.
  • Enhanced to generate anti-pad automatically when VIA is added in the PI Analyzer (PIA).
  • Enhanced visibility by adding and displaying port information to the IR-Drop analysis result image.
PollEx UPE
  • Enhanced the STEP file importer to recognize the colors of the 3D shapes.
  • Removed WRAPAROUND lead type from the Package Lead Editor.
PollEx Interface from ECAD
Cadence Allegro
  • Enhanced the Allegro importer speed.
  • Enhanced the ODB++ importer to recognize the teardrop object by utilizing “.tear_drop” property.
  • Enhanced the ODB++ import speed by optimizing the importer.
  • Enhanced the ODB++ importer to handle the layer stack-up thickness.

Resolved Issues

  • Consolidated the measure feature to the View menu in CAM.
  • Fixed a bug in the merge feature of the PCB Redmark.
  • Fixed a bug to support a new aperture file format (*.phl) created by the Zuken tool.
  • Fixed a bug in the merge feature of the DFM point tool.
  • Fixed a result display error in the Placement Keepout and Via Spacing2 items of DFM.
  • Fixed a bug in the DFE result table in which Link to ECAD with Xpedition functions did not work.
  • Fixed a bug in Logic DFE that in the process of calculating the voltage value in the Voltage Divider Logic, an error occurred depending on the Pin Type setting of the IC.
  • Fixed an issue in PI where Bundled Spice model could not be used in passive components.
  • Fixed a bug of not recognizing lowercase characters in the Spice model name of the passive component in PI.
  • Modified the Solder Quantity Calculator to recognize the figure shapes drawn as DIMENSION type.