Net Loop
This item checks whether the net has formed a loop.
- Item: Input item name.
- Net: Select a target Net Group.
- Except Net: Specific Net groups to be excluded from check.
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This section contains the user guides for the following tools: Block JIG Generator, Compare GDSII, Gerber to PCB, Make Board Paneling, Metal Mask Manager, Mounting Data Extractor, Mounting Emulator, Router-Machine JIG Generator, Solder Quantity Calculator, Soldering Pallet, Test Point Location Generator, and Underfill.
This section contains the user guides for the following tools: BOM, CAM, Component Arrangement Plan, CP, Golden Sample, Logic, PCB, Redmark+, and Worksheet Planner.
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This section contains the user guides for the following tools: DFA, DFE, DFE+, DFM, and Logic DFE.
PollEx DFA is an assembly status checking toolset for PCB design based on 3D package library.
Group the same type of objects into the same group.
This rule checks whether nets keep allowable trace widths.
This rule checks for component clearance violations when routed traces may affect the performance of nearby components.
This option helps engineers to visually differentiate specific classes of nets or net groups from the rest of nets, and identify nets with more or less than the specified number of connected components.
This rule checks for the proper use of special purpose components.
This rule checks for the validity of circuit usage and whether the routing length and clearance from driver pins are within the specified distance.
This item checks for copper area ratio on each layer.
In high power system the designer should check trace resistance in order to avoid IO-Drop problem. This rule calculates trace resistance.
This rule checks for a trace length violation.
This rule checks whether two nets are within a specified distance.
This item checks whether the net has formed a loop.
This item checks for a shielding ratio of bus group.
This item checks net connection between start pins to end pins.
This item checks whether the same net is placed close together.
This item checks whether a specified clearance requirement for the net is satisfied.
This item checks whether the filter installed in the IO terminal is well designed with low impedance.
This rule searches for routing angles that are sharper than the specified reference angle.
This item finds components that should not be connected to certain signals.
This item checks all symmetry items for uniformity of the differential pairs design environments.
This rule checks whether power pin connected to decap via separation path to form a Star Connection.
This stub rule checks unnecessary stubs for specific use cases.
This rule checks the test point/via number and clearance of net.
This item checks whether the topology required for design is used.
This item checks layers change by counting the number of Vias used in a signal net.
This rule checks routed trace widths against the specified minimum or maximum allowable widths.
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PollEx DFE+ is a fully automated SI analysis tool.
PollEx DFM is a board level manufacturability checking software.
PollEx Logic DFE is a toolset that checks electrical validity and standardizing of schematic design.
This section contains the PollEx UPE user guide.
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Discover PollEx functionality with comprehensive user guides.
This section contains the user guides for the following tools: DFA, DFE, DFE+, DFM, and Logic DFE.
This item checks whether the net has formed a loop.
This item checks whether the net has formed a loop.
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