Ground Shield

Reference

Layout Your High-Speed Nets Design short traces.

Keep the return current path as short as possible at the high-speed trace. In four or more layer boards avoid gaps or batteries of Vias within a ground plane in order to keep the loop of the current return path small. On two-layer boards provide power and ground nets close to the high-speed trace.

The smaller the return current loop the lower the electromagnetic emission. The return currents can also use the VDD system.

Figure 1. Return current loop area for multilayer boards

If fast signals are provided on the PCB, design a ground ring around each layer of your board. This ground ring should be connected by several Vias on the edge of the board together to the reference ground plane. The distance from one via to the next should not be wider than 0.5cm. This builds a reference ground ring around the board, which helps to decrease radiation from the inner layer.

Additionally, it avoids the current at the edges of the PCB can build antenna structures and radiate to the outside. If very high frequencies are transferred, the distance between the connecting Vias has to be even smaller.

The efficiency of this measure is increasing if you have more ground planes. Then the built construction describes a faraday cage for the middle signal layers.

Figure 2. Return current loop area for two-layer boards

Avoid vias in high speed traces. Vias have an additional inductance (~500 pH normal via). Avoid turns in high speed traces. Turns mean a change in the characteristic wave impedance of a trace. It is better to use 45 degree turns,or even less, than 90 degree turns.

90 degree turns mean a change in the trace’s width. Changes in the trace width cause changes in the characteristic wave impedance which will end in unwanted reflections. Provide room for a series resistor close to the driving component. If you have not set up a specific design rule yet, optimize the resistor value.

If you have two adjacent signal layers realize x-y-tracing to reduce crosstalk, place and layout decoupling capacitors.

Parallelism causes impedance discontinuities that will directly affect signal quality. In this case it also contributes to the trace-length mismatch and causes an increase in signal skew.

Figure 3. Violation of proper routing techniques

• Intel - High Speed USB Platform Design Guidelines

  
  
  Figure 4.

• Effective Inductance is calculated as:
  $$L\approx 5D\ln \left(\frac{D}{W}\right)$$
  Where,

  $D$

  Slot Length

  $W$

  Trace Width

  • Slots in a ground plane create unwanted inductance.
  • Slot inductance slows down rising edges.
  • Slot inductance creates mutual inductive crosstalk.
  • Slot width has almost no effect on signal trace inductance.
  • If the trace lies offset toward one end of the slot, the inductance is less.
  • Slots near but not overlapping a signal trace have little effect.